Going ASIC

Open source tools don't stop at doing FPGA designs. There are also flows for ASIC designs that could be done on freely available tools. Also they share common resources like Yosys synthesiz.

So why not extend GateLab features with an ASIC flow?

And best of all you just do a one click tool install from within GateLab. No fiddling around with homebrew or in the terminal app.