Features

Device families

Cologne Chip GateMate
  • CCGM1A1
  • CCGM1A2
Lattice iCE40
  • LP384
  • LP1K
  • LP4K
  • LP8K
  • HX1K
  • HX4K
  • HX8K
  • UP3K
  • UP5K
  • iCE5LP4K (Ultra)
Lattice ECP5
  • LFE5U-12F/25F/45F/85F
  • LFE5UM-25/45/85
  • LFE5UM5G-25/45/85
Gowin
  • GW1N-1
  • GW1NZ-1
  • GW1NSR-4C
  • GW1N-4
  • GW1NR-9 (3 variants)
  • GW2A-18C
  • GW2AR-18C
  • GW5A-25
AMD Xilinx
  • XC7A35T
  • XC7K325T
  • XC7S15 (through remote Vivado)
IDE features
Getting started
  • New Project from a starter board or a part
  • templates: Blinky, Button → LED, UART echo, PWM breathing LED, Counter with testbench, ROM message, HDMI colour bars, HDMI colour bars 1080p60 (Kintex-7, over spec)
  • Managed toolchain install: OSS CAD Suite, openXC7 and its Kintex-7 add-on, Claude Code
  • Connected starter boards on the welcome screen
  • recent projects with their board and chip
Editor
  • Verilog and SystemVerilog highlighting
  • constraint formats PCF, LPF, CST, CCF, XDC, QSF
  • indentation, block matching, comment toggling, find
  • Design hierarchy with help for missing modules
  • RTL viewer with SVG export
  • New File, Add Files and Folders, file actions (rename, move to trash, set as top module)
Build
  • Synthesis, place-and-route and bitstream with live console output
  • Problems in plain language with fixes
  • Report with utilization and timing per clock
  • Remote builds with Vivado or Quartus on a Linux host over ssh
Simulation
  • Icarus Verilog testbenches
  • every template has a self-checking testbench
  • Waveform viewer (radix including ASCII, markers, change jumps), Compare With
Programming
  • Program SRAM or flash
  • board detection by USB
  • Identify Chip by its JTAG ID
Pins and boards
  • Pin table with I/O standard, pull and drive
  • bank and differential-pair checks
  • package pin lists for every device
  • Board editor, import from a constraints file, save project pins as a board
  • Package index with signed board packs and library packs
Design helpers
  • Add Clock: PLL values from a frequency (iCE40, ECP5, Gowin, GateMate, Xilinx PLLE2/MMCME2)
  • Add Memory: ROM, RAM and dual-port memories from an init file (hex, bin, Intel HEX, COE, MIF), with a block RAM estimate
Library cores
  • UART, SPI, I²C
  • FIFOs, PWM, seven-segment, WS2812
  • video timing
  • TMDS encoder
  • HDMI output for 7-series, Gowin and ECP5
  • 74xx logic parts
  • the fpgacores index
Hardware debug
  • Live pin view over boundary scan, and pin captures to a waveform
  • Embedded logic analyzer: triggers, sample every N clocks, store only when, readout over JTAG or UART
  • KiCad schematic import to Verilog, with a live link to the schematic
Claude
  • Agent panel with Claude Code: edits with checkpoints and revert, attachments, sessions
  • MCP server with 28 tools: build, simulate, program, waveforms, pins, clocks, memories, the library, and the tools for live pins, the logic analyzer and schematics
Notes
  • The logic analyzer works on open-flow and openXC7 builds; Vivado and Quartus builds don't take it.
  • Live pins need the chip's boundary-scan (BSDL) file: GateLab downloads public ones from the vendor and copies AMD's from the Vivado host.
  • Git remote push is planned as a Pro feature and isn't built yet.